Tescom Halcyon 764a

The Halcyon 764A-024 Integrated T1/FT1 Test Set is a hand- held T1 Bit Error Rate Test (BERT) test set that integrates DS1/DS0 BERT test function with fractional T1 to provide testing of T1 channels and lines. The users for all models consists of DS0/DS1, Central Office (CO), Digital Operations Group (DOG), Special Services and CO/OSP construction technicians are the most common users.

The test set type is a digital full-service T1/FT1 Test Set. The 764A-024 is a favorite with technicians, managers and senior executives in many US Telcos.

The 764A-024 is the most cost-effective T1 Test Set on the market with a very low learning curve. The unit can be up and testing before competing models boot up and configure.

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SKU: 764A-024 Categories: ,

Product Overview: Tescom Halcyon 764a

Tescom Halcyon 764a Features:

  • Rugged, Lightweight & Hand-Held Integrated T1/FT1 Test Set
  • Full function T1, FT1 & DS0
  • Monitors Signaling Bits on all 24 Channels
  • DS0 Drop for Optional DDS and “Packet Mode” Stress Testing
  • Remote PC Control through GUI Interface
  • One keystroke setup for T1/FT1 Line Monitoring
  • Automatic Configuration & Pattern Recognition
  • Measures T1 Level, Frequency and Clock Slips
  • CSU, ESF, NIU, V.54 & High bit-rate Digital Subscriber Line (HDSL) ADTRAN/PairGain Loop Codes with Automatic Arming
  • Supports SF/ESF/SLC Framing with AMI/B8ZS Line Coding


Tescom Halcyon 764a Specifications

INTERFACES: Dual Bantam and RJ-48C. Two receivers for timing slip testing.

IMPEDANCES: 100 Ohms Terminated, Monitor and Bridged.


• Dimensions (L x W x H): 9.5-in x 6.33-in x 1.7-in

• Weight: 2 lbs.

• Power Requirements: 4 Watts at 115 VAC, 60Hz nominal; Output

9 VDC external Power supply. Internal 7.2 VDC NiMH pack


• T1 Interface: SIDE A – Bantam Transmit and Receive in parallel w/ RJ-45
SIDE B – (Reference Input) Bantam jacks

• T1 Signal Format: DS1 PCM, 1.544MHz ±50Hz

• Operating Modes: Full T1 or Fractional T1 Nx56/64 DS0 DS1 Signal

• Waveshape: Meets T1.403 specifications

• DS1 Line Level: 0 ±0.2dBdsx (6.0 V p-p)

• Line Codes: AMI, B8ZS

• Clocksource: Recovered from Receiver or internally generated 1.544MHz ±30Hz

• Framing: SF, ESF, SLC-96, Unframed

• FT1 Fill Date: Idle code (7F) sent in unused DS9 time slots

• Test Patterns: QRSS, 2047, 215-1, 220-1 , 223-1, 3 in 24, All 1s, All 0s, Alt 1/0, 2 in 8, 1:7, 63 and 511

• Error Injection: Single bit or streamed BER at 1e-3, 1e-4, 1e-5, 1e-6, or 1e-7

• Line Build Out: 0, -7.5, -15, 22.5dB

• DSX Pre-Equalizer: 5 steps for cable lengths to 655 feet


• BERT Analysis: Bit Errors (BE), Errored Seconds (ES), Bit >Error Rate (BER) , %Error Free Seconds (%EFS), Severely Errored Seconds (SES), %Severely Errored Seconds (%SES), Elapsed time

• LINE Analysis: T1 level, frequency, Frame Slips, Clock Slips, Framing Errors, Bipolar Violations (BPV), CRC Event Counts CRCs)

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